{"title":"A Framework for Task Mapping onto Heterogeneous Platforms","authors":"Ta-Yang Wang, Ajitesh Srivastava, V. Prasanna","doi":"10.1109/HPEC43674.2020.9286211","DOIUrl":null,"url":null,"abstract":"While heterogeneous systems provide considerable opportunities for accelerating big data applications, the variation in processing capacities and communication latency of different resources makes it challenging to effectively map the applications on the platform. To generate an optimized mapping of the input application on a variety of heterogeneous platforms, we design a flexible annotated task interaction graph based framework which 1) allows modeling of mixed CPU and GPU architectures, and 2) identifies an efficient task-hardware mapping of the input application, given the dependencies and communication costs between tasks that constitute the applications. The annotated task interaction graph (ATIG) representation captures all the information that is necessary to execute the application and the meta-data, such as performance models for estimating runtime on a target resource and communication latencies. Our framework supports solving the problem of mapping tasks in the ATIG onto available resources by including variations of greedy algorithm and LP relaxations with rounding. We show that our framework can achieve high speedup, allowing domain experts to efficiently compile a broad set of programs to parallel and heterogeneous hardware.","PeriodicalId":168544,"journal":{"name":"2020 IEEE High Performance Extreme Computing Conference (HPEC)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 IEEE High Performance Extreme Computing Conference (HPEC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/HPEC43674.2020.9286211","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
While heterogeneous systems provide considerable opportunities for accelerating big data applications, the variation in processing capacities and communication latency of different resources makes it challenging to effectively map the applications on the platform. To generate an optimized mapping of the input application on a variety of heterogeneous platforms, we design a flexible annotated task interaction graph based framework which 1) allows modeling of mixed CPU and GPU architectures, and 2) identifies an efficient task-hardware mapping of the input application, given the dependencies and communication costs between tasks that constitute the applications. The annotated task interaction graph (ATIG) representation captures all the information that is necessary to execute the application and the meta-data, such as performance models for estimating runtime on a target resource and communication latencies. Our framework supports solving the problem of mapping tasks in the ATIG onto available resources by including variations of greedy algorithm and LP relaxations with rounding. We show that our framework can achieve high speedup, allowing domain experts to efficiently compile a broad set of programs to parallel and heterogeneous hardware.