A Design of 32-Bit Embedded Microprocessor

Haimin Chen, Bin Zheng
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Abstract

A 32-bit embedded Microprocessor based on the instruction set of ARMv4T architecture is designed and implemented in this paper. It adopts five-stage pipeline, implements separate instruction and data caches, contains memory management unit, and supports coprocessor instruction. This paper proposes perfect solution for the problem of data correlation, control correlation and resource correlation emerged in the pipeline. We carry functional description for each module with Verilog HDL, and then validate its correctness through simulation and debugging. The working frequency is up to 51.3 MHz on FPGA implementation, meeting the request of high-performance embedded system.
32位嵌入式微处理器的设计
本文设计并实现了一种基于ARMv4T架构指令集的32位嵌入式微处理器。它采用五级流水线,实现独立的指令和数据缓存,包含内存管理单元,支持协处理器指令。针对管道中出现的数据关联、控制关联和资源关联问题,提出了完善的解决方案。用Verilog HDL对各模块进行功能描述,并通过仿真和调试验证其正确性。FPGA实现的工作频率高达51.3 MHz,满足高性能嵌入式系统的要求。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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