{"title":"A Design of 32-Bit Embedded Microprocessor","authors":"Haimin Chen, Bin Zheng","doi":"10.1109/ICCIIS.2010.45","DOIUrl":null,"url":null,"abstract":"A 32-bit embedded Microprocessor based on the instruction set of ARMv4T architecture is designed and implemented in this paper. It adopts five-stage pipeline, implements separate instruction and data caches, contains memory management unit, and supports coprocessor instruction. This paper proposes perfect solution for the problem of data correlation, control correlation and resource correlation emerged in the pipeline. We carry functional description for each module with Verilog HDL, and then validate its correctness through simulation and debugging. The working frequency is up to 51.3 MHz on FPGA implementation, meeting the request of high-performance embedded system.","PeriodicalId":108594,"journal":{"name":"2010 International Conference on Communications and Intelligence Information Security","volume":"4 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 International Conference on Communications and Intelligence Information Security","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCIIS.2010.45","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
A 32-bit embedded Microprocessor based on the instruction set of ARMv4T architecture is designed and implemented in this paper. It adopts five-stage pipeline, implements separate instruction and data caches, contains memory management unit, and supports coprocessor instruction. This paper proposes perfect solution for the problem of data correlation, control correlation and resource correlation emerged in the pipeline. We carry functional description for each module with Verilog HDL, and then validate its correctness through simulation and debugging. The working frequency is up to 51.3 MHz on FPGA implementation, meeting the request of high-performance embedded system.