Analysis of gate capacitance of n-type junctionless transistors using three-dimensional device simulations

Abstract

Junctionless transistors can be an excellent alternative for extremely scaled MOSFETs as they present a good behavior with no doping gradients between channel and source/drain regions. This paper aims at analyzing the gate capacitance (Cgg) of junctionless transistors dependence with the three most important technological parameters for these devices: doping concentration (ND), fin width (Wfin) and fin height (Hfin).