LVTSCR with High Holding Voltage for ESD Protection in 55nm CMOS Process

Abstract

A effective method to enhance the holding voltage of LVTSCR for electrostatic discharge (ESD) protection applications has been proposed and verified in a 55 nm epitaxial CMOS process. The proposed method improves the holding voltage by removing the STI in NW and adjusting the NMOS gate length. In addition, it can provide an good robustness for ESD protection. Measured results show that the holding voltage can be improved 66% approximately.