Managing test coverage uncertainty due to thermal noise in nano-CMOS: A case-study on an SRAM array

Abstract

From system-on-a-chip to high performance processors, SRAM is a critical component. In highly scaled CMOS devices, process variation is a major concern as it affects SRAM stability which often sets the floor on supply voltage and the ceiling on operating temperature of a semiconductor chip. Consequently, low-voltage and high temperature testing are often part of manufacturing test flow. In this paper, we show that for marginal cells, thermal noise is a major corrupting factor that affects the outcome of testing. A cell with large process variation which should ordinarily fail during memory test may pass due to impact of thermal noise at high temperature. To address this uncertainty during testing, we propose a stochastic metric for test coverage. We also propose application of N-detect and Multi-level Word Line (WL) techniques to improve test coverage based on this stochastic metric. Simulation studies on 32nm PTM models indicate varying probability of faulty bit detection across the spectrum of random thermal noise that lead to erroneous test results. Multiple accesses to each bit cell during test increases the fault coverage from -10% to near ideal 100%. Boosting WL voltage during read test and scaling it below nominal voltage during write test accelerates fault detection. Simulation of a 1KB SRAM array test case shows an improvement in fault coverage from -88% to 100% by increasing the number of detects to 100.