Exploration of reconfigurable architectures: an empirical approach

W. Ligon, U. Ramachandran
{"title":"Exploration of reconfigurable architectures: an empirical approach","authors":"W. Ligon, U. Ramachandran","doi":"10.1109/FMPC.1990.89461","DOIUrl":null,"url":null,"abstract":"An approach to designing computer architectures in which architectural features are analyzed for utility and cost with respect to the system software that uses them is applied to reconfigurable architectures. A notation for classifying reconfigurable architectures that covers three major areas of reconfigurable architecture design-processor reconfiguration, control reconfiguration, and connection reconfiguration-is presented. A simulator based on this notation, called the reconfigurable architecture workbench, is described. This has been used to study the effects of processor reconfiguration within the image-processing application domain. Experimental results showing that some types of processor reconfiguration provide significant speedup over parallel architectures without processor reconfiguration are presented. The engineering problems present in implementing processor reconfiguration are explored, and some solutions to these problems are suggested.<<ETX>>","PeriodicalId":193332,"journal":{"name":"[1990 Proceedings] The Third Symposium on the Frontiers of Massively Parallel Computation","volume":"122 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1990 Proceedings] The Third Symposium on the Frontiers of Massively Parallel Computation","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/FMPC.1990.89461","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5

Abstract

An approach to designing computer architectures in which architectural features are analyzed for utility and cost with respect to the system software that uses them is applied to reconfigurable architectures. A notation for classifying reconfigurable architectures that covers three major areas of reconfigurable architecture design-processor reconfiguration, control reconfiguration, and connection reconfiguration-is presented. A simulator based on this notation, called the reconfigurable architecture workbench, is described. This has been used to study the effects of processor reconfiguration within the image-processing application domain. Experimental results showing that some types of processor reconfiguration provide significant speedup over parallel architectures without processor reconfiguration are presented. The engineering problems present in implementing processor reconfiguration are explored, and some solutions to these problems are suggested.<>
可重构架构的探索:一种经验方法
一种设计计算机体系结构的方法应用于可重构体系结构,在这种方法中,体系结构特征被分析为与使用它们的系统软件相关的效用和成本。提出了一种可重构体系结构分类表示法,该表示法涵盖了可重构体系结构设计的三个主要领域——处理器重构、控制重构和连接重构。本文描述了一个基于这种表示法的模拟器,称为可重构体系结构工作台。这已被用于研究图像处理应用领域内处理器重构的影响。实验结果表明,某些类型的处理器重构比不重构处理器的并行架构具有显著的加速效果。探讨了实现处理器重构过程中存在的工程问题,并提出了解决这些问题的方法
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 求助全文
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信