Characterization of the faulted behavior of digital computers and fault tolerant systems

Abstract

Research that is being conducted to characterize the latent fault in digital fault-tolerant systems is addressed. A series of investigations that have led to the development of a practical high-speed gate-level logic simulator is described. The validation of the high-speed simulator, using faultable software, and hardware simulations of a prototype MIS-STD-1750A processor are discussed.<>