Delay Fault Detection Problems in Circuits Feautring a Low Combination Depth

M. Favalli
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Abstract

The growing bandwidth of digital ICs is often achieved using high speed pipelines that feature a low combinational depth. In this context, the combinational fraction of path delays becomes comparable to the timing parameters ensuring the correct logic behavior of memory elements (flip-flops and pulsed latches). In the presence of delay defects, the probability that faulty signal transitions give rise to a non-logic behavior of memory elements is no longer negligible with respect to the probability to sample a valid (correct or wrong) logic value as it is traditionally considered by the delay fault model. This phenomenon is here analyzed at the electrical level showing that it cannot be fully accounted by the path delay fault model. Hence, we propose a new fault model that accounts for memory elements possibly behaving in a non-logic way. This model has been validated at the electrical level in the presence of distributed defects and resistive opens.
低组合深度电路中的延迟故障检测问题
数字集成电路不断增长的带宽通常是通过低组合深度的高速管道来实现的。在这种情况下,路径延迟的组合分数可以与确保存储器元件(触发器和脉冲锁存器)正确逻辑行为的时序参数相媲美。在存在延迟缺陷的情况下,相对于传统延迟故障模型所认为的有效(正确或错误)逻辑值采样的概率而言,错误信号转换导致存储元件非逻辑行为的概率不再是可以忽略不计的。本文从电气层面对这一现象进行了分析,表明路径延迟故障模型不能完全解释这一现象。因此,我们提出了一个新的故障模型来解释可能以非逻辑方式行为的内存元素。该模型在存在分布缺陷和电阻开口的电水平上得到了验证。
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