DSP system architecture using signed-digit number representation

Abstract

Signed-digit (SD) arithmetic techniques are evaluated for applicability to DSP (digital signal-processing) architectures used for high-speed applications. Binary number representations limit the speed of the system due to carry propagation in addition, Residue arithmetic has been tried to alleviate this problem but its use introduces other problems in algebraic comparison, conversion, division, and floating-point representation. It is shown that signed-digit arithmetic offers the advantage of parallelism in computation without the problems associated with the residue number system. An overview of the basic features of SD arithmetic is given, followed by structures for primitive operations required for a general-purpose signal processor.<>