CIXB-1: combined input-one-cell-crosspoint buffered switch

Abstract

Buffered crossbars have been considered as an alternative for non-buffered crossbars to improve switching throughput. The drawback of a buffered crossbar is the memory amount that is proportional to the square of the number of ports (O(N/sup 2/)). This is not the main limitation when the buffer size is kept to a minimum size such that implementation is feasible. For a small buffer size, the number of ports of a switch module is not limited by the memory amount but by the pin count. We propose a novel architecture: a combined input-one-cell-crosspoint buffer crossbar (CIXB-1) with virtual output queues (VOQs) at the inputs and round-robin arbitration. We show that the proposed architecture can provide 100% throughput under uniform traffic. A CIXB-1 offers several advantages for a feasible implementation such as scalability and timing relaxation. With the currently available memory technology, a one-cell-crosspoint buffered switch is feasible for a 32/spl times/32 fabric module.