Influence of Driving Circuit Parameters and Layout Compactness on the Optimum Selection of Gate-Source Voltage Test Point for SiC MOSFETs

Abstract

Accurate measurement of the gate-source voltage for silicon carbide (SiC) MOSFET is an essential prerequisite for correctly evaluating the reliability of driving circuit. Due to the high switching speed of SiC MOSFET, it is more sensitive to parasitic parameters of circuit, the measurement error caused by traditional test methods cannot be ignored in SiC MOSFET driving circuit. In this paper, we establish the equivalent model of driving circuit considering parasitic parameters, and analyze the difference between the gate-source voltage and test voltage at different test points. Then, the influence of the driving circuit parameters and layout compactness on the test voltage error is quantitatively analyzed. And the optimum selection method of gate-source voltage test point is proposed. The experiments based on double pulse platform were given to verify the correctness of theoretical analysis and simulation results.