Design and Analysis of Multimode Signaling and Crosstalk Harnessed Signaling Technique with FPGA Implementation

Abstract

Demands on a smaller platform with higher data rate cause the density of data bus wiring increase that will result crosstalk increment and degrade the system performance. Multimode signaling and Crosstalk Harnessed Signaling (CHS) are the promising methods to mitigate crosstalk at a higher data rate but there is no proof of concept on circuit implementation on the real channel due to design complexity. Thus, in this paper, the CHS and Multimode signaling encoder and decoder are proposed to design using Field-Programmable Gate Array (FPGA) by implement in the real channel by observing the signal performance through the actual measurement. Register Transfer Level (RTL) code is implemented using logic gates for circuitry design and floating point is developed into design to indicate 32-bit binary data. The FPGA board measurement and simulation were carried out to compare the crosstalk performance between Multimode signaling and CHS. Based on the analysis, it proof-of-concept that CHS and Multimode signaling method can be designed and implemented in the FPGA. Overall, CHS is the most efficient to eliminate crosstalk with a smaller number of gates resource with a 74% reduction compared to Multimode signaling. CHS shows the best eye improvement with 15% to 28.6% eye height and eye width with 17% to 21.7% compared to the binary signaling and eye height improvement from 4.5% to 5%, 8.8% to 12% on eye width compared to Multimode signaling.