Globally asynchronous locally synchronous micropipelined processor implementation in FPGA

Abstract

This paper deals with the implementation of globally asynchronous locally synchronous (GALS), micropipelined processor in field programmable gate arrays (FPGA). Associated issues like delay model incorporating on-chip, technology independent single inverter ring oscillator (SIRO) and an unbundled datapath based on bit-encoding and return-to-zero (RTZ) schemes are also presented. Post-layout simulation results are presented to describe the behavior of various sections of the design