AArch64 Atomics: Might They Be Harming Your Performance?

Ricardo Jesus, M. Weiland
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Abstract

Atomic operations are indivisible operations guaranteed to execute as a whole. One of the most important and widely used atomic operations is "compare-and-swap" (CAS), which allows threads to perform concurrent read-modify-write operations on the same memory location, free of data races. On recent Arm architectures, CAS operations can be implemented either directly via CAS instructions, or via load-linked/store-conditional (LL-SC) instruction pairs. In this work we explore the performance of the CAS and LL-SC approaches to implement CAS operations on recent high-performance AArch64 CPUs, namely the A64FX, ThunderX2 (TX2), and Graviton3. We observe that these instructions can lead to fundamentally different performance profiles. On A64FX, for example, the newer CAS instructions---often preferred by compilers over the older LL-SC pairs---can lead to a quadratic increase in average time per successful CAS operation as the number of threads increases, whereas the older LL-SC pairs show the expected linear increase. For high thread counts, this translates into LL-SC being more than 20x faster than CAS. On TX2 and Graviton3, LL-SC can bring more conservative (but still significant) 2--3x speedups. We characterise the conditions under which each approach delivers better performance on each CPU.
原子:它们会损害你的性能吗?
原子操作是保证作为一个整体执行的不可分割的操作。最重要和最广泛使用的原子操作之一是“比较-交换”(CAS),它允许线程在没有数据竞争的情况下对同一内存位置执行并发的读-修改-写操作。在最近的Arm架构中,CAS操作既可以直接通过CAS指令实现,也可以通过加载链接/存储条件(LL-SC)指令对实现。在这项工作中,我们探讨了CAS和LL-SC方法在最新高性能AArch64 cpu(即A64FX, ThunderX2 (TX2)和Graviton3)上实现CAS操作的性能。我们观察到,这些指令可能导致根本不同的性能配置文件。例如,在A64FX上,随着线程数量的增加,较新的CAS指令(编译器通常比较旧的ls - sc对更喜欢它们)可能导致每次成功的CAS操作的平均时间呈二次增长,而较旧的ls - sc对则显示出预期的线性增长。对于高线程数,这意味着LL-SC比CAS快20倍以上。在TX2和gravon3上,LL-SC可以带来更保守(但仍然显著)的2- 3倍的速度。我们描述了每种方法在每个CPU上提供更好性能的条件。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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