Performance-controllable shared cache architecture for multi-core soft real-time systems

Myoungjun Lee, Soontae Kim
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引用次数: 2

Abstract

Multi-core processors with shared L2 caches can improve performance and integrate several functions of real-time systems on a single chip. However, tasks running on different cores increase interferences in the shared L2 cache, resulting in more deadline misses and, consequently, worse quality of real-time tasks. This is mainly because of the blind sharing of the L2 cache by multiple tasks running on different cores.We propose a novel performance-controllable shared L2 cache architecture that can alleviate these problems. First, our proposed L2 cache architecture is made to be aware of instructions/data belonging to real-time tasks by adding a real-time indication bit to each L2 cache block. Second, it can control the performance of real-time tasks and non-real-time tasks. Our experimental results show that our proposed L2 cache architecture reduces more deadline misses of real-time tasks than the conventional L2 cache architecture and partitioning schemes.
面向多核软实时系统的性能可控共享缓存架构
具有共享L2缓存的多核处理器可以提高性能,并在单个芯片上集成实时系统的多种功能。然而,在不同内核上运行的任务增加了共享L2缓存中的干扰,导致更多的截止日期错过,从而导致实时任务的质量更差。这主要是因为运行在不同核心上的多个任务盲目共享二级缓存。我们提出了一种新的性能可控的共享L2缓存架构,可以缓解这些问题。首先,我们提出的二级缓存架构通过在每个二级缓存块中添加实时指示位来感知属于实时任务的指令/数据。其次,它可以控制实时任务和非实时任务的性能。我们的实验结果表明,我们提出的二级缓存架构比传统的二级缓存架构和分区方案减少了更多的实时任务的截止日期缺失。
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