Online Constraints Update Using Machine Learning for Accelerating Hardware Verification

Abstract

The evolution of computer systems and application-specific integrated circuits led to an increase in their complexity. Consequently, verification is a vital procedure in the design process to ensure correct functionality of the designs. However, the increase in the design's complexity led to the increase in the cost and time needed for the verification in the design process. Thus, to decrease the verification process time and cost, and achieve the best coverage for the design under test; machine learning techniques are used. In this paper, a verification environment that utilizes constrained random verification technique is introduced. The environment uses dynamic reseeding and rewinding techniques. The environment is also integrated with machine learning algorithms as well to update the constraint at run time to speed up the time needed to reach full design coverage. The environment can utilize previous simulations data or prior knowledge of the design to train the model. The environment uses a different neural network topology than the state of the art. The proposed environment recorded a decrease of 83.5% in the time needed and about 60000 times decrease in the error rate for training the machine learning algorithm in comparison with the state of the art.