Online Constraints Update Using Machine Learning for Accelerating Hardware Verification

Mostafa AboelMaged, M. Mashaly, M. A. E. Ghany
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Abstract

The evolution of computer systems and application-specific integrated circuits led to an increase in their complexity. Consequently, verification is a vital procedure in the design process to ensure correct functionality of the designs. However, the increase in the design's complexity led to the increase in the cost and time needed for the verification in the design process. Thus, to decrease the verification process time and cost, and achieve the best coverage for the design under test; machine learning techniques are used. In this paper, a verification environment that utilizes constrained random verification technique is introduced. The environment uses dynamic reseeding and rewinding techniques. The environment is also integrated with machine learning algorithms as well to update the constraint at run time to speed up the time needed to reach full design coverage. The environment can utilize previous simulations data or prior knowledge of the design to train the model. The environment uses a different neural network topology than the state of the art. The proposed environment recorded a decrease of 83.5% in the time needed and about 60000 times decrease in the error rate for training the machine learning algorithm in comparison with the state of the art.
计算机系统和专用集成电路的发展导致其复杂性的增加。因此,验证是设计过程中确保设计正确功能的重要步骤。然而,设计复杂性的增加导致了设计过程中验证所需的成本和时间的增加。从而减少验证过程的时间和成本,实现对被测设计的最佳覆盖;使用机器学习技术。本文介绍了一种利用约束随机验证技术的验证环境。该环境使用动态播种和倒带技术。该环境还集成了机器学习算法,以便在运行时更新约束,以加快达到完全设计覆盖所需的时间。环境可以利用以前的模拟数据或先前的设计知识来训练模型。这种环境使用的神经网络拓扑与目前的技术水平不同。与最先进的环境相比,所提出的环境所需时间减少了83.5%,训练机器学习算法的错误率减少了约60000倍。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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