J. Fisher, R. Henz, D. Devarajan, J. Abele, S. Bibyk
{"title":"System-on-a-chip design methodologies and issues for transducer-to-pico-network applications","authors":"J. Fisher, R. Henz, D. Devarajan, J. Abele, S. Bibyk","doi":"10.1109/MWSCAS.2001.986340","DOIUrl":null,"url":null,"abstract":"The unique phenomenology of transducers complicates designing the interface of the transducer-to-pico-network protocol. This paper will explore the methodologies and issues involved in the design flow of a mixed-signal microchip through a sensor-to-pico-network design example that has been fabricated in the AMI 0.5 /spl mu/m process. The design methodologies include a careful decomposition between the digital and analog sections, as well as between the individual analog blocks, which decreases time-to-market and enhances design reuse. The fabricated design includes a 4-20 mA receiver, a second-order Sigma-Delta Modulator, fourth-order sinc filter, and an SPI block.","PeriodicalId":403026,"journal":{"name":"Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2001-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MWSCAS.2001.986340","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
The unique phenomenology of transducers complicates designing the interface of the transducer-to-pico-network protocol. This paper will explore the methodologies and issues involved in the design flow of a mixed-signal microchip through a sensor-to-pico-network design example that has been fabricated in the AMI 0.5 /spl mu/m process. The design methodologies include a careful decomposition between the digital and analog sections, as well as between the individual analog blocks, which decreases time-to-market and enhances design reuse. The fabricated design includes a 4-20 mA receiver, a second-order Sigma-Delta Modulator, fourth-order sinc filter, and an SPI block.