Efficiency ratings for VHDL behavioral models

Abstract

Due to the great complexity of VHDL models that are created today, the amount of CPU time required to simulate these models and the amount of labor required to develop these models have become critical issues. The amount of CPU time required to simulate a model can be directly influenced by the efficient use of VHDL concepts in creating the model. Research in the determination of what VHDL concepts and modeling styles are most efficient will be discussed in this paper. The development of tests that can be run on VHDL models to reveal the efficiency of the code in the form of a numerical efficiency rating will also be discussed.