Modelling The Effects Of Instruction Queue Loading On A Static Instruction Stream Micro-architecture

Abstract

Increased processor performance requires the exploitation of the parallelism that exists within the instruction stream and within the processor itself: A static instruction stream micro-architecture, CONDEL, extracts and uses the machine instruction level concurrency implicit in the instruction stream. A major source of intraprocessor parallelism is the overlap of instruction execution with instruction loading. The effect of several methods of utilizing the execution/loading parallelism within the static instruction stream machine are studied: pipelining, buffered pipelining, branch buffering and instruction load limiting. The results of incorporating the different methods into the micro-architecture are shown. In addition, the results provide a more realistic performance comparison with conventional machine designs than the upper limits presented in previous work.