Optimizing a high performance 32-bit processor for programmable logic

Abstract

Summary form only given. Altera's SOPC Builder Tool enables engineers to create tailor-made systems in an FPGA with a short development cycle; one of the most popular components in SOPC Builder is Altera's NIOS II processor. As well as ease of use and flexibility, the NIOS II family of processors offers up to 200 DMIPs of performance and can cost as little as 35 cents worth of programmable logic. This high level of performance has been achieved by tailoring the processor architecture to fully exploit the FPGA resources used. Logic, registers, memory, and multipliers have different relative costs in an FPGA when compared to an ASIC; in an FPGA, registers and memories are relatively cheap, whereas logic and in particular, the implementation of multiplexers can be of relatively high cost. These cost differences have an influence on how engineers should design for FPGAs, and defined the design of NIOS II at the architectural level. This paper presents some novel techniques for implementing multiplexers and barrel-shifters efficiently, using the NIOS II processor as an example. These techniques are useful for improving FPGA designs in general, and have typically lead to area reductions and performance improvements of 20%.