FPGA Implementation of processing element unit in CNN accelerator using Modified Booth Multiplier and Wallace Tree Adder on UniWiG Architecture

Abstract

Deep Neural Networks (DNNs) are useful for re-solving many practical problems such as traffic monitoring, vehicle detections. Among DNNs, Convolutional Neural Networks (CNNs) are generally used for image processing and video processing applications. In CNN, most of the computations are used up by convolution process. Winograd minimal filtering-based algorithm is one of the effective methods for computing convolution for small filter sizes. A prominant component of CNN accelerator design is the processing element (PE) unit which mainly comprises of the bulky multiply and accumulate (MAC) units and adder tree. It is the PE that performs the convolution operation. In this paper, new processing element has been designed using Modified Booth Encoding multiplier (MBE) and Wallace tree adders to reduce the amount of hardware resources and power consumption. This modified PE unit is implemented on an architecture known as UniWiG (Unified Winograd GEMM architecture). The proposed design reduces hardware complexity and achieves better power efficiency than the previous designs. Hardware realization of this work is done using Verilog Hardware Description Language(HDL) and tested on FPGA board.