A 2.5-GS/s 30-mW 4-bit Flash ADC in 90nm CMOS

T. Sundstrom, A. Alvandpour
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引用次数: 25

Abstract

A 2.5 GS/s flash ADC, fabricated in 90 nm CMOS, avoids traditional power, speed and accuracy trade-offs by using comparator redundancy with power-gating capabilities. Redundancy removes the need to control comparator offsets, allowing the large process-variation induced mismatch of small devices in nanometer technologies. This enables the use of small-sized, ultra-low-power comparators. Measurement results show that the ADC dissipates 30 mW at 1.2 V. With 63 gate-able comparators, the ADC achieves 4.0 effective number of bits.
2.5-GS/s 30mw 4位Flash ADC,采用90nm CMOS
2.5 GS/s闪存ADC采用90nm CMOS工艺,通过使用具有功率门控功能的比较器冗余,避免了传统的功耗、速度和精度权衡。冗余消除了控制比较器偏移量的需要,允许纳米技术中小器件的大工艺变化引起的不匹配。这样就可以使用小尺寸、超低功耗的比较器。测量结果表明,该ADC在1.2 V电压下的功耗为30mw。使用63个可门比较器,ADC实现4.0有效位数。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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