Y. Kashiwagi, Y. Tawara, H. Chaki, K. Yamada, M. Kainaga, T. Isobe
{"title":"An optimizing C compiler for the GMICRO/500 microprocessor","authors":"Y. Kashiwagi, Y. Tawara, H. Chaki, K. Yamada, M. Kainaga, T. Isobe","doi":"10.1109/TRON.1992.313267","DOIUrl":null,"url":null,"abstract":"The GMICRO/500 is a superscalar microprocessor based on the TRON specification. An optimizing C compiler for the microprocessor is under development. The compiler implements both hardware-independent optimizations and GMICRO/500-specific optimizations with a performance target of 100 MIPS at 50 MHz. The hardware-independent optimizations gave a good basis for the effective improvement of hardware/software performance. On the other hand, GMICRO-specific optimizations was a challenging problem because of the complexity of the superscalar CISC architecture. The authors describe these optimization techniques with emphasis on the implementation strategy of the GMICRO/500-specific superscalar optimization.<<ETX>>","PeriodicalId":275803,"journal":{"name":"Proceedings [1992] The Ninth TRON Project Symposium","volume":"58 11 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1992-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings [1992] The Ninth TRON Project Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/TRON.1992.313267","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
The GMICRO/500 is a superscalar microprocessor based on the TRON specification. An optimizing C compiler for the microprocessor is under development. The compiler implements both hardware-independent optimizations and GMICRO/500-specific optimizations with a performance target of 100 MIPS at 50 MHz. The hardware-independent optimizations gave a good basis for the effective improvement of hardware/software performance. On the other hand, GMICRO-specific optimizations was a challenging problem because of the complexity of the superscalar CISC architecture. The authors describe these optimization techniques with emphasis on the implementation strategy of the GMICRO/500-specific superscalar optimization.<>