Improved Synthesis of Compressor Trees on FPGAs in High-Level Synthesis

Abstract

In this paper, an approach to synthesize compressor trees in High-level Synthesis (HLS) for FPGAs is proposed. Our approach utilizes the bit-level information to improve the compressor tree synthesis. To obtain the bit-level information targeting compressor tree synthesis, a modified bitmask analysis technique based on prior work is proposed. A series of experimental results show that, compared to the existing heuristic, the average reductions of area and delay are 22.96% and 7.05%. The reductions increase to 29.97% and 9.07% respectively, when the carry chains in FPGAs are utilized to implement the compressor trees.