{"title":"New symmetric cascaded multilevel inverter with reduced number of controlled devices and low blocked voltage by switches","authors":"A. Gohari, A. Mosallanejad, E. Afjei","doi":"10.1109/PEDSTC.2017.7910377","DOIUrl":null,"url":null,"abstract":"In this paper, a new symmetric cascaded multilevel inverter with reduced number of controlled switches and the low blocked voltage by switches is presented. The proposed topology is based on the new module, which inherently produces negative levels and zero level. Each module generates 7 levels. As the number of the output voltage levels or the magnitude of the output voltage increase, the maximum value of blocked voltage of the switches does not increase. The simulation results of this inverter are performed for a 19-level inverter by using MATLAB/Simulink to verify the performance of the proposed topology. Finally, the proposed inverter is compared with other topologies to illustrate the merit of this topology.","PeriodicalId":414828,"journal":{"name":"2017 8th Power Electronics, Drive Systems & Technologies Conference (PEDSTC)","volume":"126 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 8th Power Electronics, Drive Systems & Technologies Conference (PEDSTC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/PEDSTC.2017.7910377","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6
Abstract
In this paper, a new symmetric cascaded multilevel inverter with reduced number of controlled switches and the low blocked voltage by switches is presented. The proposed topology is based on the new module, which inherently produces negative levels and zero level. Each module generates 7 levels. As the number of the output voltage levels or the magnitude of the output voltage increase, the maximum value of blocked voltage of the switches does not increase. The simulation results of this inverter are performed for a 19-level inverter by using MATLAB/Simulink to verify the performance of the proposed topology. Finally, the proposed inverter is compared with other topologies to illustrate the merit of this topology.