Analyzing and alleviating the impact of errors on an SRAM-based FPGA cluster

Abstract

This paper proposes a method to analyze the effect of manufacturing defects and soft errors: stuck-ats and bit flips, on a cluster in a Mesh FPGA architecture. The cluster reliability is evaluated with a technique that is used in case of either a single error or multiple simultaneous faults. Simulation results show that the cluster is more robust to stuck-ats than to bit-flips, whatever the configuration memory is. Then, for selective hardening against bit flips, we propose an approach to identify the critical path and the most eligible component that is likely to improve the cluster reliability.