J. Brakensiek, B. Oelkrug, M. Bucker, D. Uffmann, A. Droge
{"title":"Re-configurable multi-standard terminal for heterogeneous networks","authors":"J. Brakensiek, B. Oelkrug, M. Bucker, D. Uffmann, A. Droge","doi":"10.1109/RAWCON.2002.1030109","DOIUrl":null,"url":null,"abstract":"The next generation of mobile communication systems will lead to an integration of existing networks and access technologies, forming a heterogeneous network. New architectures are needed to serve new requirements from these new systems. The paper highlights the requirements of a reconfigurable multi-standard terminal from the physical-layer point of view. A reconfigurable architecture consisting of algorithm domain specific accelerators, allowing autonomous complex digital signal processing without interference from a microprocessor or digital signal processor, is explained. Performance comparison numbers with the latest digital signal processors show the effectiveness of the proposed architecture.","PeriodicalId":132092,"journal":{"name":"Proceedings RAWCON 2002. 2002 IEEE Radio and Wireless Conference (Cat. No.02EX573)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings RAWCON 2002. 2002 IEEE Radio and Wireless Conference (Cat. No.02EX573)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RAWCON.2002.1030109","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
The next generation of mobile communication systems will lead to an integration of existing networks and access technologies, forming a heterogeneous network. New architectures are needed to serve new requirements from these new systems. The paper highlights the requirements of a reconfigurable multi-standard terminal from the physical-layer point of view. A reconfigurable architecture consisting of algorithm domain specific accelerators, allowing autonomous complex digital signal processing without interference from a microprocessor or digital signal processor, is explained. Performance comparison numbers with the latest digital signal processors show the effectiveness of the proposed architecture.