FPGA-based hardware acceleration: A CPU/accelerator interface exploration

Abstract

One of the main challenges for embedded system designers is to find a tradeoff between performance and power consumption. In order to reach this goal, hardware accelerators have been used to offload specific tasks from the CPU, improving the global performance of the system and reducing its dynamic power consumption. Enabling the use of accelerators could become a tricky task for embedded system designers. This paper presents a complete acceleration design flow for embedded systems with an exploration of different interfaces between CPU and accelerator, analyzing their performances, resources overhead, power consumption, and implementation methods.