Extending RISC- V ISA for Accelerating the H.265/HEVC Deblocking Filter

Abstract

In this paper, we present an RISC-V based Application Specific Instruction Set Processor (ASIP) for accelerating the HEVC deblocking filter. The proposed ASIP extends the RISC-V instruction set to include new instructions specifically targeted to expedite the HEVC deblocking filter. These instructions are designed by profiling the implementation of the OpenHEVC filter. Our proposed solution improves the performance of the deblocking filter compared to the standard implementation by 11%. Furthermore, our approach can also be applied to accelerate other parts of the decoder by taking advantage of the programmability and flexibility of ASIPs.