A novel high-speed parallel sorting algorithm based on FPGA

Abstract

Efficient data sorting is important for searching and optimization algorithms in high time demanding fields such as image, multi-media data processing and radar detection. To accelerate the data sorting algorithm applied in practical radar algorithms detection such as OS-CFAR, a novel high-speed parallel sorting scheme based on field programmable gate array (FPGA) is proposed in this paper. It also provides a technique that will make the clock rate constant regardless of the length of the list that will be sorted. The paper presents new results in: 1) parallel sorting algorithms; 2) FPGA-based parallel architectures; and 3) the technique of sorting the most recently entered data items to the memory while discarding the oldest items is presented. Results obtained show a reduction in the clock rate. FPGA implementation results are presented and discussed.