Design and FPGA Implementation of a Digital Channelized Receiver

Abstract

In this paper, a digital channelized receiver is designed and implemented on FPGA. The hardware implementation is achieved through finite impulse response (FIR) filter banks, fast Fourier transformation (FFT) and random access memory (RAM). This implementation contains polyphase filter banks and bi-FFT structure in order to enhance efficiency and overlapped passband in frequency spectrum process to improve accuracy of signal restoration. The results show that a digital 8-channel receiver with 33MHz full bandwidth receiving is successfully implemented.