A Multi-Engine LUT-Based Synthesis Framework

Abstract

In this paper, we present a new synthesis framework. This framework, ASU-Synthesizer, is built for logic synthesis for LUT based FPGAs. The synthesis process is composed of logic optimization and technology mapping. We implemented the different categories of logic optimization algorithms. Then we used the well known technology mapping package, Flow-Map (Cong et al., 1996). We added to the framework, our online area estimator that we proposed before in (Hamed et al., 2004). This framework can be used to build any commercial synthesis tool for LUT-based designs