Designs of power distribution network for octa-core mobile application processor

Abstract

The high core count processor becomes the current trend to indicate the mobile devices' power. Mobile devices powered by octa-core CPUs offer faster performance, but suffer the larger dynamic voltage droops, especially for the PCB with the single-sided component placement (SSCP). Some chip-package-board co-simulations using the chip power model and full channel S-parameters were taken to evaluate the different decoupling capacitor configurations, feedback line designs, and the voltage compensation technique between the power management integrated circuit (PMIC) and the application processor (AP). Evaluation results indicated that the proposed single-ended feedback line sensed the most accurate voltage droop on the AP side than the traditional differential feedback lines did. A careful power distribution network design with the early voltage compensation technique reduced 37% of decoupling capacitor cost in the SSCP PCB and achieved the dynamic voltage droop on the AP side less than 10% of supply voltage from the PMIC.