Low power high speed D flip flop design using improved SVL technique

Abstract

D flip flops are extensively used in analog, digital and mixed signal systems. D flip flops are first choice to realize different counters, shift registers and other circuits. One major consequence of scaling of CMOS technology is leakage power. To decrease power consumption and to improve life time of battery, the voltage supplied to the given circuit during standby mode should be reduced. This paper proposes a new D flip flop design which employs improved SVL technique in order to reduce power consumption due to leakage currents in standby mode. Also the proposed design uses less number of clocked transistors, thus reduces the dynamic power consumption as well as delay compared to existing design. Proposed design achieves 60.54% reduction in power delay product in comparison with existing D flip flop design. Both existing design and proposed design are simulated using Tanner T spice tool at 45nm technology.