Design of a CMOS VCO with two tuning inputs applied for a wideband GFSK-modulated frequency synthesizer

K. Peng, C. Huang, C. Li, T. Horng, S.F. Lee
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引用次数: 5

Abstract

This paper describes the design considerations of a 2.4 GHz CMOS voltage-controlled oscillator (VCO) with two tuning inputs when used in a wideband GFSK-modulated frequency synthesizer based on a two-point delta-sigma modulation (TPDSM) architecture. One tuning input is provided mainly for the fractional-TV frequency synthesis, and the other one is for the direct GFSK modulation. In the VCO design, the tuning sensitivity for GFSK modulation is optimized including the effects of digital-to-analog converter (DAC). In addition, the size of spiral inductor in the LC tank is minimized without the cost of reducing quality (Q) factor. The implemented TPDSM-based GFSK-modulated frequency synthesizer can achieve a maximum data rate of up to 2.5 Mbps with an FSK error less than 1.4% and a phase-locked loop (PLL) settling time less than 110 /spl mu/s. The modulated frequency synthesizer with such good performances has promising application potential in a low-power solution for the enhanced data rate (EDR) Bluetooth transmitters.
用于宽带gfsk调制频率合成器的双调谐输入CMOS压控振荡器的设计
本文介绍了一种具有两个调谐输入的2.4 GHz CMOS压控振荡器(VCO)用于基于两点δ - σ调制(TPDSM)架构的宽带gfsk调制频率合成器时的设计考虑。一个调谐输入主要用于分数电视频率合成,另一个用于直接GFSK调制。在VCO设计中,考虑到数模转换器(DAC)的影响,对GFSK调制的调谐灵敏度进行了优化。此外,在不降低质量(Q)因子的代价下,使LC槽内螺旋电感的尺寸最小化。所实现的基于tpdsm的gfsk调制频率合成器可以实现高达2.5 Mbps的最大数据速率,FSK误差小于1.4%,锁相环(PLL)建立时间小于110 /spl mu/s。具有良好性能的调制频率合成器在增强数据速率(EDR)蓝牙发射机的低功耗解决方案中具有广阔的应用前景。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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