Automated Model Generation Including Variations for Formal Verification of Nonlinear Analog Circuits

Abstract

With the advancements in analog/mixed-signal (AMS) systems and continuously shrinking design sizes, there is an increased demand for reliable verification to ensure correct behavior. To overcome this obstacle, using formal verification is a promising option. We present a modeling system that automatically provides dependable set-valued models from circuit netlists in a form suitable for reachability analysis. Our method is based on local linearizations of the nonlinear circuit. Linearized locations are computed on-the-fly depending on which states are reachable to avoid the state-space explosion problem. The set-valued models include device parameter variations, modeling errors and uncertain input stimuli.