Optimum organization of SRAM-based memory for leakage power reduction

Abstract

Active power, area, architecture, and timing constraints are the major factors in choosing SRAM-based memory organization in contemporary submicron SOCs. In this paper we add the effect of SRAM organization on leakage power as another major factor to consider in selecting a cache organization. Leakage power becomes an important factor for sub 100 nm process technology especially for SRAM-based memory because of the high percentage of ideal circuit to active circuit in any given time. We present the relationship between the SRAM organization and the leakage power at the following process nodes: 32 nm, 45 nm, 65 nm, 90 nm, 130 nm and 180 nm using the predictive technology models (PTM). SPICE simulations results of leakage power versus SRAM organization for a 1-kbits SRAM design is presented in details.