FPGA Implementations of VVC Fractional Interpolation Using High-Level Synthesis

Abstract

In this paper, the first FPGA implementations of Versatile Video Coding (VVC) fractional interpolation algorithm using a high-level synthesis (HLS) tool in the literature are proposed. Three different C++ codes are developed. They implement constant multiplications with multiplication operations, addition and shift operations, and multiplierless constant multiplication algorithm, respectively. These C++ codes are synthesized using Xilinx Vivado HLS tool. The best proposed HLS implementation can process 62 full HD (1920×1080) video frames per second. It has higher performance than manual VVC fractional interpolation hardware implementations at the cost of larger area.