VTR 8

Kevin Edward Murray, Oleg Petelin, Sheng Zhong, Jia Min Wang, Mohamed Eldafrawy, Jean-Philippe Legault, Eugene Sha, Aaron G. Graham, Jean Wu, Matthew James Peter Walker, Hanqing Zeng, Panagiotis Patros, Jason Luu, Kenneth Blair Kent, Vaughn Betz
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引用次数: 16

Abstract

Developing Field-programmable Gate Array (FPGA) architectures is challenging due to the competing requirements of various application domains and changing manufacturing process technology. This is compounded by the difficulty of fairly evaluating FPGA architectural choices, which requires sophisticated high-quality Computer Aided Design (CAD) tools to target each potential architecture. This article describes version 8.0 of the open source Verilog to Routing (VTR) project, which provides such a design flow. VTR 8 expands the scope of FPGA architectures that can be modelled, allowing VTR to target and model many details of both commercial and proposed FPGA architectures. The VTR design flow also serves as a baseline for evaluating new CAD algorithms. It is therefore important, for both CAD algorithm comparisons and the validity of architectural conclusions, that VTR produce high-quality circuit implementations. VTR 8 significantly improves optimization quality (reductions of 15% minimum routable channel width, 41% wirelength, and 12% critical path delay), run-time (5.3× faster) and memory footprint (3.3× lower). Finally, we demonstrate VTR is run-time and memory footprint efficient, while producing circuit implementations of reasonable quality compared to highly-tuned architecture-specific industrial tools—showing that architecture generality, good implementation quality, and run-time efficiency are not mutually exclusive goals.
由于各种应用领域的竞争需求和不断变化的制造工艺技术,开发现场可编程门阵列(FPGA)架构具有挑战性。这与公平评估FPGA架构选择的困难有关,这需要复杂的高质量计算机辅助设计(CAD)工具来针对每种潜在的架构。本文描述了开放源码Verilog to Routing (VTR)项目的8.0版本,它提供了这样一个设计流程。VTR 8扩展了可建模的FPGA架构的范围,允许VTR瞄准和建模商业和拟议的FPGA架构的许多细节。VTR设计流程也可作为评估新的CAD算法的基线。因此,对于CAD算法比较和架构结论的有效性来说,VTR产生高质量的电路实现是很重要的。VTR 8显著提高了优化质量(减少15%的最小可路由信道宽度,41%的带宽和12%的关键路径延迟),运行时间(快5.3倍)和内存占用(低3.3倍)。最后,我们证明了VTR在运行时和内存占用方面是高效的,同时与高度调优的特定于体系结构的工业工具相比,产生合理质量的电路实现——表明体系结构通用性、良好的实现质量和运行时效率并不是相互排斥的目标。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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