A substructure method for strip level warpage simulation of a power module in assembly process

Jianghai Gu, L. Liang, Y. Liu
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引用次数: 1

Abstract

A substructural method is developed to simulate the strip level warpage of a power module in assembly process. The comparison between substructure and non-substructure methods is presented and discussed. Parametric design of experimental (DoE) study on low side (LS) and high side (HS) die thickness, epoxy mold compound (EMC) thicknenss, as well the Young's modulus Ez of prepreg and Young's modulus of EMC is conducted in the simulation.
一种用于电源模块装配过程中带材翘曲仿真的子结构方法
提出了一种模拟电源模块装配过程中带材翘曲的子结构方法。对子结构法和非子结构法进行了比较和讨论。仿真中进行了低侧(LS)和高侧(HS)模具厚度、环氧模料(EMC)厚度、预浸料的杨氏模量Ez和EMC的杨氏模量的参数化设计实验(DoE)研究。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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