Area efficient time to digital converter (TDC) architecture with double ring-oscillator technique on FPGA for fluorescence measurement application

Abstract

We present an area efficient Time to Digital Converter (TDC) yielding a high resolution of nearly 10ps. The TDC architecture reported in this paper comprises of coarse measurement using system clock and two controllable oscillators for fine resolution measurement. The reported improved resolution is attributed to the difference in their frequencies. One of the main features of the implementation is its prototyping on a low-cost FPGA.