A 28nm, 4.69TOPS/W Training, 2.34µJ/lmage Inference, on-chip Training Accelerator with Inference-compatible Back Propagation

Abstract

Previous on-chip training accelerators improved training efficiency but seldomly considered inference efficiency. We propose to convert back propagation to be compatible with inference, use interleaved memory allocation to reduce external memory access and zero-skipping loss propagation. Working at 40MHz, 0.48V core voltage, our 28nm one-core OCT chip has peak training efficiency of 4.69TOPS/W and the best inference energy of 2.34 µJ/inf/ image, 9.1× better than SoTA work.