Area and throughput trade-offs in design of arithmetic encoder for JPEG2000

Abstract

Because of serial inherence of the arithmetic encoder (AE) for the embedded block coding algorithm in JPEG2000, efficient hardware implementation of AE plays a key role in overall system throughput. In this paper, four pipelined architectures which are single-symbol coding 3-stage pipeline, single-symbol coding 4-stage pipeline, two-symbol coding 3-stage pipeline and two-symbol coding 4-stage pipeline, are investigated. Results from FPGA-based implementations show that the single-symbol coding 3-stage pipeline architecture has the best actual throughput ((133N)/(N + 2) CX/S pairs per second) and occupies the least resources (1100 ALUTs and 365 registers) in all four. Compared with several related works, our designs outperforms them in terms of tradeoff of area and throughput.