Hierarchical concepts in the design of processor arrays

Abstract

A hierarchical representation of parallel algorithms is described that can be systematically mapped onto a class of massive parallel architectures called processor arrays. A notation of hierarchical parallel programs is introduced for the representation of algorithms that can be mapped onto processor arrays. By means of a transformative approach, two provably correct program transformations are introduced to solve the problems of generating (CREATE) and of dissolving (FLATTEN) different levels of hierarchy. The program transformations CREATE and FLATTEN are formally described and explained by an example.<>