Design of heterogenous multi-processor embedded systems: applying functional pipelining

I. Karkowski, H. Corporaal
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引用次数: 25

Abstract

Practice shows that increasing the amount of instruction level parallelism (ILP) offered by an architecture (like adding instruction slots to VLIW instructions) does not necessary lead to significant performance gains. Instead, high hardware costs and inefficient use of this hardware may occur. Mapping embedded applications onto multiprocessor systems forms a very interesting extension to ILP. The authors describe their approach to the mapping of embedded programs written in ANSI C onto a pipeline of application specific processors. An efficient algorithm for functional pipelining of loops is presented. To validate its applicability the frequency tracking system is used as a case study. This typical embedded application is mapped onto a two-processor system delivering speedup of 1.88 in comparison with a highly optimized single core solution.
异构多处理器嵌入式系统的设计:应用功能流水线
实践表明,增加体系结构提供的指令级并行性(ILP)的数量(比如向VLIW指令添加指令槽)并不一定会带来显著的性能提升。相反,可能会出现硬件成本高和硬件使用效率低的情况。将嵌入式应用程序映射到多处理器系统形成了对ILP的一个非常有趣的扩展。作者描述了他们将用ANSI C编写的嵌入式程序映射到应用程序特定处理器的管道的方法。提出了一种高效的循环函数流水线算法。以频率跟踪系统为例,验证了该方法的适用性。这个典型的嵌入式应用程序被映射到一个双处理器系统上,与高度优化的单核解决方案相比,它的加速提高了1.88。
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