Power-combined multipliers at 60 GHz based on fundamental frequency vector modulation

Abstract

High output power multiplier is necessary for local oscillator source of terahertz communication. However, single multiplier chip power-handling capability is limited by understandably low efficiency level and other technical constraints. To enhance the power-handling capabilities, we propose a power-combined multiplier architecture based on fundamental frequency vector modulation utilizing double chips. By tuning input fundamental frequency phase to compensate the fabrication and assembly error, we can increase the output power by 3 dB compared with single multiplier at 60 GHz.