{"title":"A rapid carrier recovery loop for direct conversion receivers","authors":"S. Tatu, E. Moldovan, K. Wu, R. Bosisio","doi":"10.1109/RAWCON.2003.1227917","DOIUrl":null,"url":null,"abstract":"Direct conversion receiver (DCR) is an alternative wireless architecture to the well established super-heterodyne, particularly for low-power and low-cost terminals [A. A. Abidi, December 1995]. A new Ka-band high-speed direct conversion wideband six-port receiver was designed for wireless communications. This QPSK six-port receiver operates using analog signal processing (ASP). The QPSK DCR consists of a receiver front-end, a QPSK demodulator and a carrier recovery module. A reverse modulation loop (RML) was used to provide a rapid carrier recovery. The maximum bit rate, around 120 MB/s, is limited by the speed of the base-band circuits. The new hardware receiver is proposed for use in wide Ka-band wireless mass-market QPSK communications such as LMDS services. Bit error rate (BER) results versus the noise and reference signal phase shift are presented.","PeriodicalId":177645,"journal":{"name":"Radio and Wireless Conference, 2003. RAWCON '03. Proceedings","volume":"2015 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2003-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Radio and Wireless Conference, 2003. RAWCON '03. Proceedings","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RAWCON.2003.1227917","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6
Abstract
Direct conversion receiver (DCR) is an alternative wireless architecture to the well established super-heterodyne, particularly for low-power and low-cost terminals [A. A. Abidi, December 1995]. A new Ka-band high-speed direct conversion wideband six-port receiver was designed for wireless communications. This QPSK six-port receiver operates using analog signal processing (ASP). The QPSK DCR consists of a receiver front-end, a QPSK demodulator and a carrier recovery module. A reverse modulation loop (RML) was used to provide a rapid carrier recovery. The maximum bit rate, around 120 MB/s, is limited by the speed of the base-band circuits. The new hardware receiver is proposed for use in wide Ka-band wireless mass-market QPSK communications such as LMDS services. Bit error rate (BER) results versus the noise and reference signal phase shift are presented.