Spiking analog neuron circuit design, analysis, and simulation

Abstract

A transistor-level analog circuit design of a spiking neuron is proposed. The circuit was simulated using using BSIM3 0.8 /spl mu/m geometry MOS transistor parameters provided by MOSIS. Most of the circuits work in the MOS sub-threshold region of operation to achieve very low power consumption. Supply voltage was set at 2.8 V As examples of neural networks, feed-forward and feed-back neural networks capable of recognizing black and white patterns were simulated using a transistor level circuit simulator Static power dissipation of the proposed neuron was estimated to be approximately 180 pW for the dendrite and 56 pW for the soma. In the dynamic mode, energy consumption was estimated to be 5.1 pJ (dendrite) and 1.2 pJ (soma) per activation. An analog HDL simulator was also used to simulate neural network behavior for the larger neural network examples.