Tool for system design verification

Abstract

An approach is presented for automatic formal verification of digital hardware designs using Prolog. Validation of design correctness is made by formal proof as an alternative to the traditional approach which utilizes simulation. A hardware design methodology based on this framework entails: writing a specification of required design, designing a circuit intended to implement it, and proving mathematically that the design meets its specification. Prolog is used both as a representational language for describing the design specification and implementation and also as an inference mechanism for proving its functional correctness. A developed verification system has enough domain specific and general mathematical knowledge to perform the proofs largely automatically. Designs can be handled from the transistor level up to the architectural levels. Some large designs, including a simple computer, have already been verified.<>