Analysis of the Possibility of Implementing Synchronization Devices Operating on OFDM Technology on CMOS Transistors with Submicron Design Standards in High-Speed Data Transmission Systems

Abstract

The article provides an analysis of circuit solutions and the results of circuit simulation of some options for constructing a phase locked loop (PLL), which contains the following components: phase detectors, voltage-controlled oscillators, passive and active low-pass filters and a frequency divider. All PLL components implemented as part of the classical CMOS technology and circuitry. The proposed solutions on CMOS transistors with submicron design standards allow achieving a significant increase in operating frequencies. Our results and developed models will allow us to evaluate the synchronization problems at the very first stages of the development of synchronization devices for orthogonal frequency division multiplexing (OFDM) technology and to choose the most effective methods for ensuring synchronous operation of the transmitter and receiver.